G.Skill Trident Z5 Neo RGB, DDR5, 32 GB, 6000MHz, CL30
Mobo X670 AORUS ELITE AX (rev. 1.1)

pascaltec wrote:

Indeed Ryzen with two dies (above 12 cores) are non-NUMA (Non-Uniform Memory Access). Multiple sockets Xeon platforms are also non-NUMA.
There is a switch in the some BIOS to make the OS (Operating System) aware of non-NUMA.

In the case of Ryzen made of 2 dies, the aim of thread pinning is to pin threads to the cores of the same die, hence the task's threads share the same L3 cache of one die. The same hold for 7900x.

If threads are spread on the two dies (NO pin-thread), communicating between the L3 caches (between the two dies) through the infinity fabric is less efficient than sharing one L3 cache of one die.

You have confusingly used too many nons. NUMA already means non-uniform memory access,
so when you say "non-NUMA" you effectively say "uniform memory access",
which is not the case for multi-socket systems.

In NUMA systems, each socket has a block of RAM beside the socket which is fastest
for that socket because those data transfers do not pass through a bus switch.
From this the meaning of locality is clear.

AMD processors with CCX have multiple NUMA domains for each socket because of the cache on each CCX.