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Message boards : Number crunching : Intels new cpu's with efficiency cores and performance cores.

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Profile Elftron
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Message 153704 - Posted: 31 Jan 2022 | 4:49:19 UTC

I will be looking to get a new CPU (Primegrid mostly use) soon and I have been looking at the new intel 12th Gen CPU range. Does anyone know whether an efficiency core in terms of primegrid will work as well as a full performance core.

I might be jumping the gun a bit but looking at best bang for buck.

Elftron
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Message 153922 - Posted: 5 Feb 2022 | 14:56:57 UTC
Last modified: 5 Feb 2022 | 15:11:58 UTC

I was just thinking about this myself Elftron.
Prior to reading this I noticed an example (although I'm only guessing the ration was 1:1 and no m/t) between a 10980XE and a 12990K.

The 10980XE is an 18 core cpu & the 12900k is a core core (3.2GHz (5.2GHz max clock speed), 16 Cores (8 Performance-cores, 8 Efficient-cores), 24 Thread (16 on Performance-cores, 8 on Efficient-cores)

Crunching MEGA -
Mr 288Larrson has the 12900K. 1,438.59 - 1,777.20 to complete PPS-MEGA tasks.
Nick's 10980XE - 2,475.84 - 3,017.68 to complete MEGA tasks.

http://www.primegrid.com/results.php?hostid=1101267&offset=0&show_names=0&state=2&appid=21

http://www.primegrid.com/results.php?hostid=1090395&offset=0&show_names=0&state=2&appid=21

Could that be a fair representation of how good the 12 series is? The only bit I don't know is how many cores are crunching tasks. The 10980 is easy - 18. The "P's & "E" core I'm stumped on.
Mr Larsson's might only be using 8 cores?
It's pretty fast either way!

This should be an interesting topic because I'm sure a lot of use are wondering.

It's also worth noting that there's stories of AVX-512 being disabled for Alder Lake and other stories of mobo manufactures allowing bios updates to enable AVX-512.

https://www.techspot.com/news/92830-intel-reportedly-disabling-avx-512-instruction-set-alder.html#:~:text=In%20brief%3A%20Intel%2012th%20Gen,to%20enable%20this%20instruction%20set.&text=A%20new%20report%20claims%20Intel,512%20won't%20work%20anymore.

https://www.tomshardware.com/news/msi-reenables-avx512-support-on-alder-lake-cpus

Any info on that would be great appreciated.

EDIT - ** I found out AVX-512 only works on the "P" cores so that's 8 cores running at a time vs 16.
Someone can tell us what that equates to over a 24hr period I guess.
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Profile ChookaProject donor
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Discovered 2 mega primesFound 1 prime in the 2019 Tour de PrimesFound 5 primes in the 2020 Tour de PrimesFound 4 primes in the 2021 Tour de PrimesFound 5 primes in the 2022 Tour de PrimesFound 2 mega primes in the 2022 Tour de Primes321 LLR Turquoise: Earned 5,000,000 credits (5,148,143)Cullen LLR Turquoise: Earned 5,000,000 credits (5,348,560)ESP LLR Turquoise: Earned 5,000,000 credits (5,373,643)Generalized Cullen/Woodall LLR Turquoise: Earned 5,000,000 credits (5,072,649)PPS LLR Sapphire: Earned 20,000,000 credits (45,319,283)PSP LLR Turquoise: Earned 5,000,000 credits (7,765,873)SoB LLR Turquoise: Earned 5,000,000 credits (5,915,028)SR5 LLR Turquoise: Earned 5,000,000 credits (5,312,387)SGS LLR Turquoise: Earned 5,000,000 credits (5,138,512)TRP LLR Turquoise: Earned 5,000,000 credits (9,029,146)Woodall LLR Turquoise: Earned 5,000,000 credits (8,900,442)321 Sieve (suspended) Ruby: Earned 2,000,000 credits (2,279,140)Generalized Cullen/Woodall Sieve (suspended) Turquoise: Earned 5,000,000 credits (6,057,633)PPS Sieve Double Silver: Earned 200,000,000 credits (309,103,845)AP 26/27 Sapphire: Earned 20,000,000 credits (20,987,213)GFN Emerald: Earned 50,000,000 credits (93,484,959)WW Double Bronze: Earned 100,000,000 credits (173,576,000)
Message 153927 - Posted: 5 Feb 2022 | 16:18:30 UTC
Last modified: 5 Feb 2022 | 16:19:18 UTC

der8auer has a good video.

https://www.youtube.com/watch?v=_qoOqAjhegE
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Message 153969 - Posted: 6 Feb 2022 | 18:49:06 UTC

That video is old. Looks like Intel decided to disable AVX-512 on 12th-gen completely. Although certain motherboards might re-enable it.

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Message boards : Number crunching : Intels new cpu's with efficiency cores and performance cores.

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