It uses AVX on Intel CPUs. I'm not 100% sure on the details but on current AMD CPUs performance is significantly lower as they're hardware limited, regardless of the instruction support.

Yeah, I'm aware of that, that's why I need to half my cores to get use of the AVX "advantage". It worked so far for the 321 LLRs and I noticed a big difference in the runtimes.
Maybe I was too fast and it's just because these Cullens are so long and the % shown isn't yet representative enough, will see how it looks in a day.
Just to make sure - which would make my request from the first post useless of course - does every subproject uses AVX when possible? I'm not sure anymore... ;-)

The exact same LLR app is used for 321, Cullen, ESP, PSP, PPS, PPSE, PPS Mega, SoB, SR5, SGS, TRP and Woodall. Sieve jobs use a different program entirely. While the LLR app may have different names because of how BOINC works, it's bit-for-bit identical across all the above projects. So they all behave identically as far as AVX usage.

To my understanding, the gwnum library used by LLR is optimised to use the fastest code available for each processor type. To say if it is using AVX or not is almost not the point, as long as it is using the correct optimisations for the processor to give best overall performance.

I vaguely recall when AMD implemented something, I think it was FMA instructions, they were tested and showed to provide no throughput benefit. It was safer not to use them at all. Current AMD FPU units simply don't have the power in them, made worse that you only typically get one FPU per two marketing cores. Everyone is waiting to see how Zen might change that.

Everyone is waiting to see how Zen might change that.